A conventional current switch circuit is shown in FIG. 1. The circuit 10 has two inputs, inn and inp for receiving a differential voltage. For the purposes of description throughout this specification, including in the claims, when the voltage at the inp input is higher than the voltage at the inn input, the differential voltage is deemed to have a positive polarity. By contrast, when the voltage at the inn input is higher than the voltage at the inp input, the differential voltage is deemed to have a negative polarity.
As further shown in FIG. 1, in the current switch circuit 10, the base of a first PNP input transistor Q1 is coupled to receive the inn input, and the collector of the first PNP input transistor Q1 is coupled to the V.sub.EE power rail. Similarly, the base of a second PNP input transistor Q2 is coupled to receive the inp input; the collector of the second PNP input transistor Q2 is also coupled to the V.sub.EE power rail.
A pair of input clamp diodes D9 and D10, connected in parallel in opposing polarity, couple the emitters of the first and second PNP input transistors Q1, Q2. Thus, the emitters of the first and second PNP input transistors Q1, Q2 are never more than one diode in voltage apart. That is, provided a large enough differential voltage at the inn and inp inputs, only one of the PNP input transistors Q1, Q2 is on at any one time.
The emitter of the first PNP input transistor Q1 is voltage coupled to the base of a first NPN switch transistor Q3 through a first voltage biasing diode D7. A first biasing current I1, provided from a second biasing current source transistor Q121, which is coupled to the anode of first voltage biasing diode D7, ensures that the first voltage biasing diode D7 and the first input transistor Q1 remain conducting. The collector of the first NPN switch transistor Q3 is coupled to the V.sub.CC power supply rail.
In a similar fashion, the emitter of the second PNP input transistor Q2 is voltage coupled to the base of a second NPN switch transistor Q4 through a second voltage biasing diode D8. A second biasing current 12, provided from a second biasing current source transistor Q120, which is coupled to the anode of second voltage biasing diode D8, ensures that the second voltage biasing diode D8 and the second input transistor Q2 remain conducting.
The emitters of the first and second NPN switch transistors Q3, Q4 are coupled together to receive a first switch current 13, from a first switch current sink transistor Q132. The collector of the second NPN switch transistor Q4 is coupled to sink the first switch current 13 from a first switch output OUT1 when the voltage across its base-emitter junction is such that second NPN switch transistor Q4 is conducting. Otherwise, the collector of the first NPN switch transistor Q3 is coupled to the V.sub.CC rail to provide a path for the first switch current 13 when the voltage across its base-emitter junction is such that the first NPN switch transistor Q3 is conducting. As will be discussed in detail below, only one of the NPN switch transistors Q3, Q4 is conducting at any one time.
As further shown in FIG. 1, the emitter of the first PNP input transistor Q1 is also voltage coupled to the base of a first PNP switch transistor Q5 through the first voltage biasing diode D7. The collector of the first PNP switch transistor Q5 is coupled to the V.sub.EE power supply rail. Similarly, the emitter of the second PNP input transistor Q2 is voltage coupled to the base of a second PNP switch transistor Q6 through the second voltage biasing diode D8.
The emitters of the first and second PNP switch transistors Q5, Q6 are coupled together to receive a second switch current I4 from a second switch current source transistor Q124. The collector of the second PNP switch transistor Q6 is coupled to sink the second switch current 14 from a second output OUT2 when the voltage across its base-emitter junction is such that second PNP switch transistor Q6 is conducting. Otherwise, the collector of the first PNP switch transistor Q5 is coupled to the V.sub.EE rail to provide a path for the second switch current I4 when the voltage across its base-emitter junction is such that the first PNP switch transistor Q5 is conducting. As will be discussed in detail below, only one of the PNP switch transistors Q5, Q6 is conducting at any one time.
Furthermore, only one of the second NPN switch transistor Q4 and the second PNP switch transistor Q6 is conducting at any one time.
The conventional circuit 10 operates generally as follows. In response to a differential voltage applied to the differential inputs inn, inp, a voltage difference is formed across the clamp diodes D9, D10. For ease of discussion, voltage differences will herein be referred to by the number of "diode" drops or increases.
Taking first the case where the differential voltage has a positive polarity (i.e. when the voltage at the inp input is higher than the voltage at the inn input), the second input transistor Q2 is off. Thus, the emitter of the second input transistor Q2 is one diode (across the second clamp diode D10) above the emitter of the first input transistor Q1, or two diodes above the input inn. Furthermore, the base of the second NPN switch transistor Q4 is one more diode drop (across the second voltage biasing diode D8), or three diode drops above the input inn.
The base of the first input NPN switch transistor Q3 is one diode (across the first voltage biasing diode D7) above the emitter of the PNP input transistor Q1, or two diodes above the inn input. The emitter of the first NPN switch transistor Q3 is also at two diodes above the inn input. Therefore, the first NPN switch transistor Q3 is off.
The second NPN switch transistor Q4, however, has its base at two diode drops from the emitter of the first input transistor Q1 (or three diodes above the inn input and its emitter at one diode from the emitter of the first input transistor Q1 (or two diodes above the inn input. Thus, the current I3 is sunk from the first switch output OUT1.
By contrast, the second PNP switch transistor Q6 is off, so the both the base and the emitter of the second PNP switch transistor Q6 are at three diodes above the inn input.
The first PNP switch transistor Q5 is on, and it conducts the current I4 to the V.sub.EE rail.
In the case where the differential voltage has a negative polarity (i.e. when the voltage at the inn input is higher than the voltage at the inp input), the first input transistor Q1 is off. Thus, the emitter of the first input transistor Q1 is one diode (across the first clamp diode D9) above the emitter of the second input transistor Q2, or two diodes above the inp input. Furthermore, the base of the first NPN switch transistor Q3 is one more diode drop (across the first voltage biasing diode D7), or three diodes above the inp input.
The base of the second PNP switch transistor Q4 is one diode drop (across the second voltage biasing diode D8) from the emitter of the second PNP input transistor Q2, or two diodes above the inp input. Since the second NPN switch transistor Q4 is off, the emitter of the second NPN switch transistor Q4 is also at two diodes above the inp input.
The first NPN switch transistor Q3, however, has its base at three diodes above the inp input and its emitter at two diodes above the inp input. Thus, the current I3 is conducted to the V.sub.CC rail.
By contrast, the first PNP switch transistor Q5 is off, so the both the base and the emitter of the first PNP switch transistor Q5 are at three diodes above the inp input.
The second PNP switch transistor Q6 is on, and it sources the current I4 into the OUT2 output.
The conventional current switch circuit 10 has the problem that the capacitances associated with the switch current source transistors Q132 and Q124 slow the switching speed of the switch transistors Q3, Q4, Q5, and Q6.
Furthermore, it is desirable to provide a current switch which requires fewer current sources and less circuitry.